Method and apparatus for simulation of a multi-processor circuit

Abstract

Multiple processor circuit simulator comprising a debugger interface, a synchronizer, a RISC processor simulator, a vector processor simulator, a shared memory, a co-processor interface module and an events module. The multiple processor simulator tightly couples the RISC processor simulator and vector processor simulator into a single executable process and a single address space. The synchronizer interleaves simulation of instruction execution between multiple processor simulators. The synchronizer determines which processor simulator to execute based on a furthest-behind clocking scheme. The clocking scheme is implemented by comparing the values held in clock simulators corresponding to the processor simulators.