Memory cell allowing write and erase with low voltage power supply and

Abstract

In a nonvolatile semiconductor memory device, a memory cell array includes memory cell transistors and cell select transistors corresponding to the memory cell transistors, respectively. A memory cell SG decoder supplies a potential to a cell select line corresponding to the selected row. The cell select transistor opens and closes a conduction path of a current flowing between a bit line and a source line through the memory cell transistor in accordance with the potential on the cell select line. As a result, an influence by a leak current flowing from the unselected memory cell transistor in a read operation is suppressed.