The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2000

Filed:

Mar. 26, 1997
Applicant:
Inventor:

Je-ik Kim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T / ; H04N / ;
U.S. Cl.
CPC ...
348845 ; 3488452 ; 348699 ; 382236 ;
Abstract

A high-speed motion vector decoding circuit which decodes a motion vector formatted according to the MPEG-2 standard. The motion vector decoding circuit implements a motion vector decoding method on dedicated hardware including a pipeline structure. The hardware includes a parameter store for storing the input motion vector decoding parameters, that is, a motion vector range determination code, a motion vector code, and a motion vector residual code. The hardware also includes a motion vector decoder for storing motion vector to be decoded as a previous motion vector and decoding the motion vector using the parameter stored in the parameter store and the previous motion vector, a dual primer for receiving the previous motion vector stored in the motion vector decoder and generating a predetermined number of dual motion vectors, and a motion vector controller for controlling the operations of the decoder via the input parameters, and selecting and outputting the previous motion vector or the dual motion vector, as a finally decoded motion vector. A six-clock period of time is needed to decode one motion vector, and a 6+(n-1)-clock period of time is needed to decode n motion vectors via the pipeline structure, which enables the decoding circuit to be applied to a high-speed system such as a high-definition television.


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