The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2000

Filed:

May. 12, 1997
Applicant:
Inventor:

Richard H Womack, Albuquerque, NM (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327538 ; 327543 ;
Abstract

An amplified MOS biasing apparatus and method for avoiding latch-up within an integrated circuit. An amplifier receives a plurality of voltages and multiplies the voltages by a gain so as to generate a plurality of amplified voltages. A comparator compares the plurality of voltages and generates signals indicating which is greatest and which is smallest. A switch connects the greatest of the voltages to N-wells in PMOS transistors and connects the smallest of the voltages to P-wells in NMOS transistors to discourage parasitic diodes, within the PMOS and NMOS transistors, from conducting excessive amounts of current.


Find Patent Forward Citations

Womack, Richard. (2000). Amplifier mos biasing circuit for a avoiding latch-up (U.S. Patent No. 6014053). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6014053

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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