The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2000

Filed:

Jan. 31, 1996
Applicant:
Inventors:

Prasenjit Biswas, Saratoga, CA (US);

Shumpei Kawasaki, Palo Alto, CA (US);

Norio Nakagawa, Tokyo, JP;

Osamu Nishii, Tokyo, JP;

Kunio Uchiyama, Tokyo, JP;

Assignee:

Hitachi Micro Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
712222 ; 712203 ;
Abstract

A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.


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