The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2000
Filed:
Apr. 14, 1998
Sagar Pushpala, Sunnyvale, CA (US);
Abdalla Naem, Sunnyvale, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A method is provided involving re-slicing a wafer after dual-side alignment and processing has been performed. This procedure provides twice as many processed electronic devices without increasing the number of loading, processing and unloading procedures performed or the total number of substrates used. Another method is provided for creating two processed chips by attaching two conventional substrates, processing IC's on each of the two exposed, polished sides and then detaching the substrates. This technique reduces the number of loading, processing and unloading procedures required to produce a given number of IC chips by half. An apparatus and further method provides two different subsystems of a single IC processed on opposite sides of the same chip. Such a device saves cost by using fewer substrates to make the same number of chips. Also, the method performs loading, processing and unloading procedures half as much to produce a given number of IC's. The apparatus is an integrated circuit chip comprising two subsystems, each processed on a different side of the same silicon substrate. Sizes of chips is thereby decreased due to the smaller width of the substrate that results after processing.