Cross-triggering cpus for enhanced test operations in a multi-cpu

Abstract

Two or more cross-triggering CPUs for enhancing test operations in a multi-CPU computer system. Method for using same. A first CPU has a first trigger input, a first trigger output and first internal test-facilitating circuitry operable to assert the first trigger output when a first event occurs within the first CPU, and also operable to take a first test-facilitating action response to an assertion of the first trigger input. A second CPU has a second trigger input, a second trigger output and second internal test-facilitating circuitry operable in the same way. The first trigger output is coupled to the second trigger input, and the second trigger output is coupled to the first trigger input. (The arrangement may be extended to include any number of CPUs.) The trigger input and trigger output in each CPU may both be coupled to a bidirectional chip pad in the CPU, and the bidirectional chip pads of each CPU coupled together. The internal test-facilitating circuitry may include a programmable state machine configured to accomplish the test-facilitating action responsive to the trigger input, and to generate the trigger output responsive to the detection of events occurring within the CPU. State machine output devices may include: trap circuitry for causing the CPU to execute a trap routine; clock hold circuitry for causing the system clock within the CPU to hold; sample-on-the-fly circuitry for latching the state of a plurality of nodes within the CPU; or counter circuitry for counting events.