The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 1999

Filed:

Nov. 08, 1995
Applicant:
Inventors:

David T DeRoo, St. Joseph, MI (US);

Mark D Nicol, Stevensville, MI (US);

David J DeLisle, Berrien Springs, MI (US);

Saifuddin Fakhruddin, St. Joseph, MI (US);

Lloyd W Gauthier, Austin, TX (US);

Robert A Kohtz, St. Joseph, MI (US);

Assignee:

Packard Bell NEC, Sacramento, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711103 ; 711152 ; 711170 ; 712 37 ;
Abstract

An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.


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