Method and system for supporting non-deterministic burst lengths in a

Abstract

A method and system is provided for avoiding data bus contention between EDO DRAM banks during a burst cycle to a memory page crossing a memory bank boundary. Each memory bank has output drivers configured to selectively drive data on a common data bus. The disclosed method and system contemplate decoding memory addresses into bank select signals and comparing the bank select signals for the current memory cycle to the state of the bank select signals in the previous cycle. If the current access is to a different bank, then the cycle is delayed and a disable signal is pulsed active to the EDO DRAM, disabling the output drivers. The memory page is kept open in the memory banks to allow bursts across bank boundaries. The current cycle is then allowed to continue to completion and data bus contention is avoiding while crossing the bank boundary.