The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 1999

Filed:

Mar. 27, 1998
Applicant:
Inventor:

Hiroyuki Kobatake, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365201 ; 36518529 ; 36523004 ;
Abstract

A checkerboard data pattern is written in a semiconductor memory with a simple arrangement. First, memory cell transistors M00-M77 are erased. A test signal TS is turned to 'L,' an address ax0 to '1,' write signals D0, D2, D4 and D6 to '1.' This causes '1' to be written in the memory cell transistors even-numbered in both the rows and columns. Then, the test signal TS is turned to 'L,' an X address ax0 to '0,' write signals D1, D3, D5 and D7 to '1.' This causes '1' to be written in the memory cell transistors odd-numbered in both the rows and columns. Thus, the checkerboard can be written with a simple arrangement by activating only the least significant bit ax0 of X addresses ax2-ax0.


Find Patent Forward Citations

Kobatake, Hiroyuki. (1999). Test method and circuit for semiconductor memory (U.S. Patent No. 6009027). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6009027

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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