The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 1999

Filed:

Jul. 28, 1997
Applicant:
Inventors:

Robert Tamlyn, Jericho, VT (US);

Edward Butler, Chandler, AZ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365201 ; 36523005 ; 36518907 ; 371 211 ; 371 2231 ;
Abstract

The present invention discloses a system and method of testing semiconductor memory devices formed as integrated circuits on semiconductor substrates. The present invention allows parallel testing of arrays using only one input/output (I/O or DQ) to write to the arrays and only two DQs to read from the arrays. The broad search should be directed to methods of compressing the time and number of I/O's required for testing wide, high pin count, or highly partitioned memory arrays. The specific method of this invention comprises simultaneously writing the same test bit to each array, simultaneously reading a common address from each array and comparing the output of each array to report a fail if all outputs are not the same.


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