The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 1999
Filed:
Oct. 23, 1997
Kazumasa Kioi, Fujiidera, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A MOS logic circuit is charged by adiabatic charging, and is composed of a clamp circuit having a pair of PMOS transistors, and two functional circuits, each having at least one NMOS transistor, a gate electrode of each of the NMOS transistors being an input node, one terminal of each functional circuit being connected to a common constant-voltage power source, and the other terminal of each functional circuit being connected to a drain electrode of the corresponding PMOS transistor, thus forming an output node. A substrate electrode of each of the NMOS transistors making up the two functional circuits is cross-connected to the output node of the other functional circuit. In this way, even in the HOLD operation, in which both input nodes fall to low level, the NMOS transistor which is to output low level becomes depletion mode, and the outputting operations are stabilized without increasing circuit size.