Optimization of logic gates with criss-cross implants to form asymmetric

Abstract

An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack. Adjacent gate stacks can have asymmetric channels with the same dopant concentration, or may be fabricated having different concentrations by varying the height of the photoresist mask to achieve a wider ion-implantation beam and thus form a higher dopant concentration on the target channel region. The optimized gates with higher dopant concentration improves off-state leakage current (10.sup.-8 amps/micron), but reduce the gate speed. The gates may also be optimized for gate speed and power consumption by producing uniformly doped asymmetric gates (20-50 pico-second fall time delays being achievable).