The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1999
Filed:
Nov. 06, 1996
Motoki Higashida, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
Buffer trees are detected in an inputted logic circuit and sets of driver gates included in the respective buffer trees are made (in Step 102). A set of gates relating to more than one buffer tree, i.e., a group of gates to be optimized, is detected (in Step 103). The groups of gates to be optimized are classified according to the symmetry in logic structure (in Step 104). Each group of gates to be optimized is extracted (in Step 105). The buffer trees are restructured so as to be in a symmetrical relation with each other (In Step 106). Through the above process, the buffer trees are optimized to be in a symmetrical relation of logic structure. Thus, the method of optimizing the logic circuit to ensure reduction in routing area, total length of interconnections and delay of the layout after placement is accomplished.