The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1999
Filed:
Apr. 03, 1998
Sean B Mulholland, Colorado Springs, CO (US);
James D Allan, Colorado Springs, CO (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A robust system for entering a test mode in an integrated circuit, for example, a memory device, greatly eliminates the probability of unintentionally entering the test mode, yet provides a system of access through a precise address and control pin sequence. By using an existing control pin present on the integrated circuit as a clock signal input for a series of latches, the present scheme sets up a number of address with predetermined values in order to create a key that is correct only if all the addresses are at the correct values. The key, combined with the clock signal input, allows a test mode enable signal to pass through each latch in a series. By further requiring that the address sequence for the key be input during an otherwise 'illegal' operation for the integrated circuit, the present scheme further ensures that unintentional entry to the test mode is avoided.