Image processing apparatus having improved memory access for high speed

Abstract

An image processing apparatus suitable for three-dimensional high speed image processing can be realized by improving the memory address control and the access method, that is, by improving the data transfer speed between the image memory and the other unit. The image processing apparatus comprises the pixel forming unit (1) for forming frame data for each pixel; an image memory (2) constructed by a plurality of banks (3, 4) to which row addresses are inputted through a row address input system (6) and column addresses are inputted through a column address input system (7); and the DRAM controller (5) for controlling the image memory (2). The DRAM controller (5) controls the image memory (2) in such a way that the screen is divided into a plurality of rectangular regions so that the frame data of one rectangular region can be stored in one page of the image memory (2); the frame data in the adjoining rectangular regions are allowed to correspond to the two different banks (3, 4) of the macro cell; and the column addresses can be generated continuously when any of the banks is being accessed, so that any addresses can be accessed continuously in the same page. Further, the DRAM controller (5) controls the address sequence predicting circuit (8) in such a way that the banks to be accessed in the future can be accessed immediately after the bank to be accessed is switched.