The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1999
Filed:
Feb. 25, 1998
Brian L Brown, Sugar Land, TX (US);
David R Brown, Sugar Land, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A clock circuit including a first delay circuit comprising an input terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals. The input terminal is coupled to the first input terminal of a first logic circuit in the series and the output of the first logic circuit is coupled to the second input terminal of a second logic circuit in the series. The output of the second logic circuit is coupled to the first input terminal of a third logic circuit in the series, and subsequent logic circuits in the series have alternately the first or second input terminal coupled to the output terminal of an immediately preceding logic circuit in the series. The circuit also includes a second delay circuit comprising an output terminal and a series of logic circuits, each of the logic circuits including an output terminal and first and second input terminals. The output terminal of the first logic circuit in the series is coupled to the second input terminal of a second logic circuit in the series. The output of the second logic circuit is coupled to the first input terminal of a third logic circuit in the series. Subsequent logic circuits in the series have alternately the first or second input terminal coupled to the output terminal of an immediately preceding logic circuit in the series. The circuit also includes a control circuit coupling the output terminals of the series logic circuits in the first delay circuit to corresponding input terminals of the series logic circuits in the second delay circuit.