The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 1999

Filed:

Jul. 17, 1998
Applicant:
Inventors:

Freeman Zhong, Fremont, CA (US);

William E Miller, Los Gatos, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327270 ; 327276 ;
Abstract

An apparatus for and method of reducing electromagnetic interference of an integrated circuit by providing multiple choking levels are disclosed. A choking circuit includes a choking level select signal generator, a pulse choking circuit connected to the choking level select signal generator, and a modulation control circuit connected to the pulse choking circuit. The choking level is increased when modules of the integrated circuit are less active, which reduces electromagnetic interference. The choking level is decreased when modules of the integrated circuit are more active, which maintains the voltage supplied to the power bus above a desired level.


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