The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1999
Filed:
Dec. 04, 1997
Gene M Amdahl, Atherton, CA (US);
Other;
Abstract
A multiple chip self-aligning clock distribution system. The clock signal provided to any given chip is delayed by the on-chip distribution time of every other chip with which it is to be synchronized. Equal delay paths are added to each chip which provide a delay equal to the clock distribution delay of the chip. The equal delay paths can comprise a series of logic gates, such as for example inverters. The clock distribution delay of the equal delay path is designed to be equal to the clock distribution delay of the clock distribution tree on the chip. For each chip to be synchronized, the clock signal is routed through an equal delay path on each of the other chips to be synchronized before being coupled to the clock distribution input terminal of the destination chip. The number of equal delay paths that is included on each chip is a function of the number of chips to be synchronized. 'N' equal delay paths are used where the number of chips is greater than 2.sup.N-1 and is less than or equal to 2.sup.N. Process variations that affect the clock distribution delay of the logic on the chip are likely to have a similar effect on the clock distribution delay of the equal delay path. This minimizes the effect of process variations on the clock alignment in the system.