The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 1999

Filed:

Mar. 26, 1998
Applicant:
Inventors:

Shinichiroh Ikemasu, Kawasaki, JP;

Kazuhiro Mizutani, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438241 ; 438253 ; 438549 ;
Abstract

A semiconductor device comprises a semiconductor substrate; a transfer transistor including a gate electrode formed on the semiconductor substrate through a gate insulation film, and a first diffused layer formed in the semiconductor substrate on both sides of the gate electrode; an insulation film which covers an upper surface of the transfer transistor and in which a contact hole reaching the first diffused layer is opened; a capacitor formed on the insulation film and connected to the first diffused layer through the contact hole; a second diffused layer formed in the semiconductor substrate below the contact hole and being the same conduction type as the first diffused layer; and a third diffused layer formed in the semiconductor substrate below the contact hole, formed extending to a region which is deeper than the first and the second diffused layers, and having the same conduction type as the first diffused layer. The semiconductor device of this structure can solve both problems of unstable impurity diffusion from the storage electrode into the semiconductor substrate, which results from an interface state, and mitigation of the electric field mitigation in the storage node, whereby the DRAM can have improved data retention characteristics.


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