System and method for covering illegal states in a programmable gate

Abstract

A programmable gate array (PGA) according to the present invention includes a plurality of state machine logic blocks and a plurality of error detecting logic blocks. Each state machine logic block of the plurality of state machine logic blocks produces a respective state with the plurality of state machine logic blocks in combination producing a system state. The plurality of state machine logic blocks are interconnected to execute logic programmed logic functions, such functions employed by a system within which the PGA resides. The error detecting logic blocks are interconnected to detect errors in the system state and to produce an error signal upon detection of an error in the system state. The error signal serves to reset operation of the plurality of state machine logic blocks. The plurality of state machine logic blocks may be one-hot encoded wherein, during non-error states, only one of the states produced by the plurality of state machine logic blocks is logic high. In such case, the plurality of error detecting logic blocks detects an error in the system state when more than one of the states produced by the plurality of state machine logic blocks is logic high or when none of the plurality of state machine logic blocks is in a logic high state. In producing the error signal, the plurality of error detecting logic blocks may be connected in a multi-level hierarchy.