Error correction and detection system for mass storage controller

Abstract

Data read out from a mass storage unit are provided as a serial data stream in parallel to both a buffer memory and an error detection circuit. The read out data are stored within the buffer memory. At the same time, the error detection circuit performs an error detection operation on the serial data stream read out from the mass storage unit. The error detection operation consists of dividing a segment of the serial data stream corresponding to a data block by the error check polynomial and determining the remainder of the division operation. The remainder from this initial error division operation is stored. Error correction is then performed on the data stored in the buffer memory, for example using a Reed-Solomon code. When erroneous bytes are identified by the error correction circuitry, the error equations are solved to determine the error pattern and then the erroneous byte is overwritten in the buffer memory. The location of the erroneous byte within the serial data stream, along with the error pattern of the byte, are then used to calculate a correction to the remainder from the initial error division by the error check polynomial on the read in data stream. Error correction continues until the remainder is reduced to a zero value. At this point, it is assumed that all of the errors have been corrected and the data stored in the buffer memory is provided to the data bus of the host computer.