Special instruction register including allocation field utilized for

Abstract

A method and system in a superscalar data processing system are disclosed for the temporary designation of a physical register as a particular general register. The data processing system is capable of processing multiple instructions during a single clock cycle. Physical registers are established. None of the physical registers are initially designated as a particular general register. No general registers exist which are initially designated as particular general registers. For each of the multiple instructions, a determination is made as to whether the instruction is a load register instruction. If the instruction is a load register instruction, a determination is made as to whether the instruction is associated with a logical register name. Each one of the logical register names identifies a different general register. In response to the instruction being associated with a logical register name which identifies a particular general register, one of the physical registers is temporarily designated as the general register which is identified by the logical register name associated with the instruction. A special instruction register is established for each of the multiple instructions. Each special instruction register includes a plurality of fields including an allocation field. A first indicator is stored in the allocation field for special instruction registers associated with load instructions. A second indicator is stored in the allocation field for special instruction registers which are not associated with load instructions.