The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 1999

Filed:

Jul. 08, 1998
Applicant:
Inventor:

Kazuyoshi Shinada, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ; G11C / ;
U.S. Cl.
CPC ...
36518504 ; 365201 ; 365226 ; 371 211 ; 711163 ;
Abstract

A testing pad is connected to an EEPROM through a wiring layer of a security circuit and a test circuit, while a testing pad is connected to the EEPROM through a wiring different from the wiring layer and the test circuit. A polysilicon pattern is connected to the wiring layer, and an n-type diffusion region is connected to the wiring. A tunnel insulation film having a thickness of about 100 .ANG. is formed between the polysilicon pattern and the n-type diffusion region. After a test for the function and stored information of the EEPROM is completed, a voltage, which is not lower than a predetermined voltage applied during the test, is applied between the testing pads to break the tunnel insulation film, thereby making the polysilicon pattern and n-type diffusion region conductive.


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