The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 1999
Filed:
Feb. 25, 1999
John F Carver, Hobe Sound, FL (US);
Elliott Energy Systems, Inc., Stuart, FL (US);
Abstract
A DC to DC converter includes a first transistor having a first power terminal connected to one side of a DC power supply and a second power terminal connected to one end of an inductor. A second transistor has a first power terminal connected to the other end of the inductor and a second power terminal connected to the other side of the DC power supply. A pair of capacitors is connected in series and defined therebetween a node which is connected to a ground potential. A third transistor has a first power terminal connected to the one end of the inductor and a second power terminal connected to one end of the pair of capacitors. A fourth transistor has a first power terminal connected to the other end of the pair of capacitors and a second power terminal connected to the other end of the inductor. Each transistor includes a diode connected between the first power terminal and the second power terminal thereof. Each diode is oriented to conduct current in a direction opposite its corresponding transistor. A controller is connected to a control terminal of each transistor for controlling the switching thereof. The DC to DC converter can be operated to increase or decrease a DC voltage between the DC power supply and the pair of capacitors connected in series. Connecting the ground potential to the node between the pair of capacitors avoids generating large potential differences between the DC power supply and the pair of capacitors.