The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 1999
Filed:
Oct. 17, 1997
ZhiYuan Zou, Fort Collins, CO (US);
Hoang P Nguyen, Fort Collins, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
The present invention provides for ESD protection while allowing the use of an input signal that is higher than V.sub.DD. The present invention preferably includes a protection device and a delay circuit coupled to an input pad and to a ground reference. The protection device is a preferred silicon controlled rectifier, and the delay circuit is preferably a low pass filter RC circuit that includes a resistor and a capacitor. A node associated with the delay circuit is coupled to circuitry of an integrated circuit. The circuitry has associated therewith at least one gate oxide breakdown voltage. A gate oxide breakdown voltage is prevented from being applied to the circuitry of the integrated circuit. When an ESD voltage is applied to the input pad, the voltage at that pad ramps or increases quickly. The delay circuit prevents the node from ramping as quickly by delaying the ramping or increasing of the node voltage. This delay provides time for the protection device to turn on and sink the ESD current.