The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 14, 1999

Filed:

Oct. 24, 1997
Applicant:
Inventors:

William P Evans, Catonsville, MD (US);

Eric Naviasky, Ellicott City, MD (US);

Patrick Farrell, Baltimore, MD (US);

Anthony Caviglia, Marriotsville, MD (US);

John Ebner, Baltimore, MD (US);

Hugh Thompson, Baltimore, MD (US);

Hao Tang, Silver Spring, MD (US);

Assignee:

G2 Networks, Inc., Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L / ;
U.S. Cl.
CPC ...
327144 ; 327163 ;
Abstract

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.


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