The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 1999
Filed:
Jul. 01, 1996
Shinji Matsushima, Yokohama, JP;
Seiichi Kawano, Sagamihara, JP;
Masayoshi Nakano, Yokohama, JP;
Takashi Inui, Yokohama, JP;
International Business Machines Corporation, Armonk, NY (US);
Abstract
An information processing system that can reduce the operating frequency of a CPU, or halt the operation of the CPU, at an adequate timing, even when the system is engaged in exchanging data with another independent apparatus (e.g., another PC) via a communication port (a serial port or a parallel port), or when a communication application is being executed. The system has (a) a CPU that operates in a normal mode, in a power saving mode in which less power is consumed than is required in a normal mode, or in a stop mode in which operation is completely halted; (b) at least one peripheral device; (c) a bus employed for communication between the CPU and the peripheral device; (d) a communication port, physically connected to another independent apparatus, for performing data transfer; (e) a bus cycle detector monitoring a bus cycle on the bus; (f) a state detector determining an operational mode of the CPU in response to a detection by the bus cycle of access of the communication port; (g) a signal generator providing, when the state detector ascertains that the operational mode is to be the power saving mode, a control signal to the CPU to set the CPU to the power saving mode; and (h) a CPU operation halting signal completely halting an operation of the CPU when the state determination means ascertains that the operational mode is to be the stop mode.