The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 1999
Filed:
Jun. 26, 1997
Masahiko Toyonaga, Hyogo, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An LSI layout design technique is disclosed which has the ability to satisfy LSI timing constraints in a short processing time. A netlist descriptive of a target circuit that is designed is fed to a computer, and a flip-flop netlist representing information about connections among flip-flops relating to the timing constraints, is generated from the netlist. Such a flip-flop netlist is generated by clustering using a flip-flop as a seed. According to the generated flip-flop netlist, each flip-flop is placed and a flip-flop region to place therein a cell relating to a flip-flop is determined. A cell relating to a corresponding flip-flop is placed in a flip-flop region and the cell arrangement is improved throughout the placement region. Based on the improved cell arrangement, a layout is designed.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile