The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 1999
Filed:
Sep. 02, 1994
Daniel R Edwards, Ypsilanti, MI (US);
George R Reasoner, Jr, Tecumseh, MI (US);
Gerald R Smith, Farmington, MI (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
An arrangement for extracting and processing image data to form an array of re-scaled pixel data, this arrangement being part of a Normalizer/Scaler stage in an image lift/processing system, and including: a scaler for storing N different selectible scaling algorithms; a scaler-output; an input for receiving scanned lines of pixel data and feeding it sequentially line-by-line, pixel-by-pixel to the scaler, the input including 'scale factors' for selecting an algorithm; while the scaler includes a mapping stage for executing a two-dimensional mapping of adjacent pixel values and adjacent scanline values; this arrangement also including a command store for storing scaling algorithms, with a command register input for the scale factors. Preferably the scaler also includes a First ROM for storing pixel values at prescribed addresses; a Second ROM for similarly storing previous pixel values, being input in parallel with the First ROM; a Latch to which the ROMs are output; and a pixel Counter reset with each new scan line; with a 'current pixel' value input to a prescribed address in the First ROM, along with a 'pixel count' number from the Counter, plus an associated scale factor; with an Adder interposed between the ROMs and the Latch to execute addition mapping.