The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 1999
Filed:
Apr. 13, 1998
Chen Ling, Sunnyvale, CA (US);
Siu-han Liao, Hsinchu, TW;
Holtek Semiconductor Inc., Hsinchu, TW;
Abstract
A new structure of a triple-well non-volatile semiconductor memory cell array and a method of fabricating the memory arrays are described. The circuit layout of the memory array not only includes the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of contact windows, further increasing the packing density of the memory array. The key point of the method is the triple-well formation inside the silicon substrate that lowers the operational voltage of periphery circuit. Furthermore, there are two additional isolation regions between two adjacent metal lines, which can minimize the possibility of cross talk due to shirking spacing.