The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1999

Filed:

Nov. 17, 1997
Applicant:
Inventor:

Shinichiro Tomisawa, Gifu-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
714766 ; 714805 ;
Abstract

An error correction decoder for correcting errors in digital data includes an address generation circuit capable of generating addresses for accessing a first buffer memory and a second buffer memory. The first buffer memory preferably stores user data, and the second buffer memory stores parity code data associated with the user data. An input controller receives input data and stores the input data in the first and second buffer memories in accordance with the addresses generated by the address generation circuit. An error correction circuit receives user data and associated parity code data, performs error correction, and rewrites the corrected data and parity code data back to the respective memory areas. An output controller then read the error-corrected user data from the first buffer memory.


Find Patent Forward Citations

Tomisawa, Shinichiro. (1999). Error correction decoder including an address generation circuit (U.S. Patent No. 5996107). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5996107

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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