The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 1999
Filed:
Apr. 28, 1997
Applicant:
Inventors:
Donald Evans, Williston, VT (US);
Luigi Ternullo, Jr, San Jose, CA (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
714719 ; 714 71 ; 365201 ;
Abstract
The present invention is a system and method of testing logic circuits in memory of an integrated circuit in a fraction of the time. The present invention discloses a system and method to allow testing imbedded array logic blocks in parallel, rather than sequentially. The present invention allows for the testing of multiple logic blocks associated with different memory or column locations at the same time. This technique allows for reduction in test time by a factor of X, where X is the number of rows or columns or memory cells feeding logic.