The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1999

Filed:

Apr. 17, 1998
Applicant:
Inventors:

Hunter Ledbetter Scales, III, Austin, TX (US);

Keith Everett Diefendorff, Los Gatos, CA (US);

Brett Olsson, Cary, NC (US);

Pradeep Kumar Dubey, New Delhi, IN;

Ronald Ray Hochsprung, Los Gatos, CA (US);

Assignees:

Apple, Cupertino, CA (US);

IBM, Armonk, NY (US);

Motorola Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
712-5 ; 712-7 ; 712-4 ;
Abstract

The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input vectors as specified by the control vector, and further stores the result of the operation as the output operand in an output register. The control vector consists of sixteen indices, each uniquely identifying a single byte of input data in either of the input registers, and can be specified in the operational code or be the result of a computation previously performed within the vector registers. The specification of the control vector allows a vector-matrix operation to be performed on the input vectors by rearranging or replicating the input operand bytes in the bytes of the output register as a function of the control vector. This system provides a highly efficient register loading mechanism for data vectors misaligned in memory, and allows the computation of a serially dependent chain of binary functions within the vector registers.


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