The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1999

Filed:

Sep. 23, 1998
Applicant:
Inventors:

Tiao-Hua Kuo, San Jose, CA (US);

Yasushi Kasa, Cupertino, CA (US);

Nancy Leong, Sunnyvale, CA (US);

Johnny Chen, Cupertino, CA (US);

Michael Van Buskirk, Saratoga, CA (US);

Assignees:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Fujitsu Limited, Kanagawa-Ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518511 ; 36518513 ; 36523003 ;
Abstract

A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.


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