The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1999

Filed:

Feb. 02, 1998
Applicant:
Inventors:

Tadashi Ogasawara, Akita, JP;

Kaneo Mori, Akita, JP;

Masaaki Taniguchi, Akita, JP;

Masahiko Konno, Akita, JP;

Dai Matsuoka, Arlington, MA (US);

Assignee:

TDK Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01C / ;
U.S. Cl.
CPC ...
338 21 ; 338274 ; 338308 ; 338332 ; 257536 ; 296101 ;
Abstract

A laminated chip varistor has a varistor element including at least one varistor layer and at least two inner electrodes which are laminated alternatively, and outer most layers comprising the same material as the varistor layer; and terminal electrodes electrically connected to the inner electrodes each formed at each of the both edge portions of the varistor element; wherein a surface roughness (R) of the varistor element is in the range of 0.60 to 0.90 .mu.m.


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Ogasawara, Tadashi. (1999). Laminated chip varistor and production method thereof (U.S. Patent No. 5994995). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5994995

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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