The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1999

Filed:

Sep. 21, 1998
Applicant:
Inventors:

Jayarama N Shenoy, Santa Clara, CA (US);

Paul Findley, Cupertino, CA (US);

Assignee:

VLSI Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257659 ; 257691 ; 257664 ;
Abstract

A circuit arrangement for a flip chip utilizes fixed potential shield traces between various signal traces in a redistribution layer to decrease coupling impedances and crosstalk within the layer. In particular, by orienting a fixed potential shield trace between a pair of signal traces and/or between a pair of differential trace pairs, capacitive coupling between the traces is greatly reduced, thereby permitting the signal traces to be routed closer to one another than would be possible if the shield trace was omitted. Often, minimum line width and spacing design rules may be met to ensure maximum circuit density for the redistribution layer and the associated device interconnections, and without concern for excessive adverse effects due to capacitive coupling between traces in the redistribution layer.


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