The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 1999
Filed:
Oct. 11, 1996
Charles E Stroud, Lexington, KY (US);
Miron Abramovici, Murray Hill, NJ (US);
Lucent Technologies Inc., Murray Hill, NJ (US);
University of Kentucky Research Foundation, Lexington, KY (US);
Abstract
A method of testing field programmable gate arrays (FPGAs) includes the step of configuring programmable logic blocks of the FPGAs for completing a built-in self-test. Specifically, the FPGA under test may be configured to act as an iterative logic array wherein a first group of programmable logic blocks are configured as test pattern generators, output response analyzers and helper cells, and a second group of programmable logic blocks are configured as blocks under test. The blocks under test are then repeatedly reconfigured in order to completely test each block under test in all possible modes of operation. The first and second groups of programmable logic blocks are then repeatedly rearranged so that all the programmable logic blocks are established as blocks under test at least once. Following the rearrangement, the repeated reconfiguration of the blocks under test is performed once again.