Test clock modes

Abstract

An electronic system such as a processor or computer system includes circuitry that supports a plurality of clock modes. The clock modes may be used for, for example, testing for critical paths. The clock modes include a variety of clock signal variations that may be utilized such as cycle stretch clock mode, pulse or delay fault mode, and stop mode which provide substantial flexibility in support of a multitude of tests. In one embodiment, a processor of an electronic system includes test clock mode circuitry to support and utilize test clock modes without dependence on an external bypass clock signal operating at processor operational frequencies. Furthermore, the processor implements the test clock modes at full processor operational frequencies. Additionally, a phase-locked loop is utilized to synchronize test mode clock signals with a reference clock signal to, for example, facilitate realistic operational conditions and acquisition of accurate test results. Additionally, in some test clock modes, the phase-locked loop may be synchronized prior to issuing test clock signals to, for example, further support realistic processor operational conditions during, for example, testing operations.