Processor for executing an instructions stream where instruction have

Abstract

A processor that executes an instruction stream having at least one compressed register field allows for smaller programs and greater processing speed. The instructions have at least one n-bit register number field and at least one m-bit register code field, where n is less than m. The n-bit register number field is capable of designating any register in a set of working registers. The m-bit register code field is capable of designating any register of a subset of the working registers. The m-bit register code may designate a source or destination register of the current instruction, a source or destination register of the last instruction, or a destination register of the second to last instruction. An instruction fetch section of the processor fetches the instruction words from memory. As part of the instruction decoding process, the m-bit register code field is passed to a register designation code conversion, or register mapping, section where the m-bit register code is converted into an n-bit register number. Various embodiments of the register mapping section include: (1) a fixed mapping such that identical inputs always cause identical outputs; (2) a conversion table in which all or part of the table's content may be updated by execution of either a special or regular instruction.