Method and system for hdl global signal simulation and verification

Abstract

The notion of global signals (e.g., global set/reset and global tristate) is of significance to programmable logic user throughout the design process. Regardless of whether the HDL designer explicitly describes the use of a global signal, they are present in the implemented device since they are an integral part of the initialization and start-up process. This may lead to mismatches between the Register Transfer Level (RTL) simulation and the timing simulation. While a methodology for verifying the functionality of global signals is available for schematic design entry, none exists for HDL design tools. A verification method for HDL designers is disclosed providing access to all the functionality relating to global networks currently available to the schematic designers and allowing reuse of the testbench without losing HDL code portability.