Internal clock generation circuit for synchronous semiconductor device

Abstract

A synchronous semiconductor device being operated in synchronism with an external clock signal includes an internal clock controller and an internal clock generator. The internal clock controller is responsive to an externally applied signal indicative of a beginning of an operation and generates an internal control signal in synchronism with the external clock signal. The internal control signal is only activated for a predetermined time interval long enough to carry out the operation. The internal clock generator serves to generate an internal clock signal synchronized with the external clock signal while the internal control signal is activated. An internal buffer circuit is operated in synchronism with the internal clock signal. Accordingly, power consumption can be reduced while in a standby mode.