Global wire management apparatus and method for a multiple-port random

Abstract

A global wire management apparatus and method for a multiple port random access memory (RAM) is disclosed. The RAM includes an array of stacked dual memory cell structures each including a common row/column decoder disposed between an upper memory cell and lower memory cell. The upper memory cell is situated adjacent upper transfer gate circuitry, and the lower memory cell is situated adjacent lower transfer gate circuitry. The decoder circuit is oriented vertically in the middle of the dual memory cell structure so that the true and complement decoder outputs may be fed upwards and downwards to the upper and lower transfer gate circuits. Wiring of the upper and lower transfer gate circuits may be effected completely at the local interconnect layer. Each of the write ports of the common decoder includes a NAND gate, an inverter, and a transfer gate for each of the upper and lower memory cells for controlling the transfer of data to the upper and lower memory cells. The disclosed global wiring management methodology provides an approach for reducing the number of global interconnect wires in a multiple port random access memory cell by sharing various wiring channels between memory cells. Such an approach allows a number of the memory cell global signal interconnects to be moved from the global wiring plane to the local wiring plane.