Synchronous semiconductor memory device operable in a burst mode

Abstract

Predetermined bits of an address signal taken into an address register are taken into a burst address counter and are changed in synchronization with a clock signal. The address bits from the burst address counter are applied to a block decoder for selecting a memory sub-array from the plurality of memory sub-arrays. A block address and the memory sub-array to be selected change at every clock cycle. An operation frequency of data read circuits provided for the respective memory sub-arrays can be made lower than a frequency of the clock signal. Memory cell data can be read out accurately even in a high-frequency operation.