Write multiplexer apparatus and method for multiple write port

Abstract

An improved apparatus and method for facilitating multiple write port access to a programmable memory apparatus is disclosed. A memory array, such as a random access memory array, includes a plurality of memory cells. A number of write ports are coupled to the memory array, each of which provides write access to individual memory cells of the memory array. Each of the write ports includes a NAND gate, an inverter, and a transfer gate. The NAND gate includes first and second inputs respectively coupled to a write row select line and a write column select line, and an output coupled to the input of the inverter and a first control input of the transfer gate. The output of the inverter is coupled to a second control input of the transfer gate. The input of the transfer gate is coupled to a data line, and the output of the transfer gate is coupled to a memory cell of the memory array. In response to appropriate logic levels on the write row select line and write column select line, data on the data input line is transferred through the transfer gate and written into the memory cell. Reduced node capacitance at the input of the memory cell and an increase in memory cell write speed are realized by implementing the disclosed write port circuitry.