The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 1999
Filed:
Mar. 28, 1997
Applicant:
Inventors:
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 98 ; 326 81 ; 326 97 ; 326121 ;
Abstract
A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An output of the logic gate 1 is an input to the logic gate 2. No level converter is arranged between the logic gates 1 and 2, and therefore, the power dissipation of the CMOS logic circuit is small. The CMOS logic circuit is designed according to a method that satisfies timing requirements and maximizes the number of logic gates that operate on the lower supply voltage (VDDL).