The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 23, 1999
Filed:
Oct. 31, 1997
Richard Steven Griph, Mesa, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A high speed, low power 3-2 adder (300, 500) with latchable outputs comprises a most significant bit (MSB) adder circuit (100) and a least significant bit (LSB) adder circuit (200). MSB adder circuit (100) includes three differential data inputs (A1, B1, and C1), a latch enable input (LE1), three separate bias points, and an MSB output. In addition the LSB adder circuit includes three differential data inputs (A2, B2, and C2), a latch enable input (LE2), three separate bias points and a LSB output. Internal latch circuits (172, 272) and latch enable circuits (174, 274) are provided in each adder stage. Internal latch enable inputs are connected in parallel in one configuration. Separate latch enable inputs are provide in a second configuration. Separate bias points are also provided in each adder stage.