Data processing device having accelerator for digital signal processing

Abstract

A data processing device uses a processor such as a central processing unit and a special-purpose hardware circuit, such as an accelerator for accelerating the software operation using the operation program of the processor by replacing the software operation partially by the hardware. A practical application of this processor arrangement is found in mobile communication terminal devices including a digital cellular portable telephone in which a digital signal processor of a mobile communication terminal device operates in association with an accelerator for accelerating specific signal processings such as waveform equalization. The processor provides input data to the accelerator and the results of operation by the accelerator are output to a register or memory based on a cycle of operation to be read periodically by the processor. When the processor operates in association with the accelerator and is interrupted, the data output to the memory of the accelerator cannot be read by the processor and a clock control circuit is used for stopping the internal clock signal of the accelerator for stopping its operation. This avoids the potential for the operation of the accelerator to overwrite the output stored in the output register of the accelerator before it is read by the processor. The processor cannot read the output register of the accelerator while it processes an interrupt or when it loses ownership of the bus connecting the processor to the accelerator.