The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 16, 1999
Filed:
Apr. 13, 1998
Applicant:
Inventor:
Emilio Miguel Yero, Aix-En-Provence, FR;
Assignee:
SGS-Thomson Microelectronics S.A., Gentilly, FR;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518521 ; 3651852 ; 365205 ;
Abstract
Disclosed is a memory read circuit with a device to limit the precharging of the bit lines. The circuit includes a portion forming a current mirror and providing furthermore for a controlled precharging of the bit line and of the reference line in limiting the precharging potential to a borderline value referenced with respect to the ground. The circuit may be applied to non-volatile (EEPROM, Flash EPROM) memories, and especially memories supplied with low voltages.
Yero, Emilio. (1999). Memory read circuit with precharging limitation device (U.S. Patent No. 5986937). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5986937
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile