The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 1999

Filed:

Jan. 26, 1998
Applicant:
Inventors:

Raul Salvi, Boca Raton, FL (US);

Gustavo D Leizerovich, Miami Lakes, FL (US);

Peter J Yeh, Coral Springs, FL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L / ; H03L / ;
U.S. Cl.
CPC ...
331 17 ; 331 10 ; 331 / ; 3311 / ; 331185 ; 327159 ; 327160 ;
Abstract

A method and apparatus for biasing the voltage controlled oscillator (VCO) (110) of a Phase Locked Loop (PLL) (100) includes a bias circuit (114) providing a peak minimum/maximum voltage detector (202) tied to the control line (116) of the PLL (100). During operation, the detector (202) detects a minimum or maximum voltage on the VCO control line (116) as the bias control voltage (118) applied to the VCO (110) is varied. Detection of such a minimum or maximum voltage is equivalent to the detection of a minimum or a maximum frequency, which in turn equates to the detection of an optimal bias condition for noise.


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